1. Field of the Invention
This invention relates to a convolution arithmetic circuit for a digital signal processing system such as a digital filter.
2. Description of the Prior Art
In recent years, widespread use has been made of digital recording and playback units such as PCM recorders or DAD (digital audio disc) players utilizing PCM (pulse code modulation) techniques to enable audio equipment to have as high fidelity as possible. FIG. 1 is a diagram of a digital recording and playback system according to prior art configurations. An analog signal, such as an audio signal, is input through terminal 11 and lowpass filter 12 removes unwanted high-frequency components from that signal. The output of filter 12 is supplied to sample-hold circuit 13, which samples the analog signal at a sampling frequency prescribed for the unit (e.g., 44.1 KHz in the case of a DAD player), for conversion into a digital signal by A/D (analog to digital) converter 14. Digital processing circuit 15 adds an error correction code and digital modulation to the digitized signal which is then recorded on a recording medium 16 such as a tape or a disc.
The original digital signal is recovered by digital demodulation processing circuit 17 which demodulates the playback signal from recording medium 16 and performs error correction for errors resulting from, for example, defects in the recording medium 16. The digital signal is extracted as a continuous analog signal, i.e., the original audio signal, from the output terminal 20, after removing the high-frequency noise component by low-pass filter 19, and after step-wise conversion to an analog signal by D/A (digital to analog) converter 18.
When the analog signal is recovered by sampling using this digital recording and playback unit, high-frequency components biased about the sampling frequency are generated resulting in a high-frequency distribution near the upper limit of the original frequency band. Low-pass filter 19 must therefore have a steep filter characteristic to remove these components.
If a digital filter 21 is interposed after the A/D converter 14 or before the D/A converter 18 to remove the high-frequency components in the digital signal stage, the filter characteristic of the low-pass filter 19 need not be so steep.
Generally, there are two operations for providing digital data with a filtering characteristic. One is in the frequency domain and another is in the time domain. The former filtering operation is accomplished first by a fast Fourier translation (FFT) of an input digital data sequence x(t) in the time domain into digital data X(w) in the frequency domain. Then, by multiplying the digital data X(w) with a transmission function G(w) having a desired characteristic in the frequency domain, and finally by applying an inverse fast Fourier translation (IFFT) of the product Y(w)=X(w).G(w), an output data sequence y(t) is generated in the time domain. This digital filtering operation, however, cannot take place in real time if the input digital data sequence x(t) occupies a relatively long time. Furthermore, the FFT and IFFT hardware required is very complicated and large.
Another filtering operation uses a convolution algorithm between the input data sequence in the time domain x(t) and an impulse response sequence g(i) (i=0, 1, . . . , m). The convolution algorithm for this filtering operation is expressed as follows: EQU y(t)=.SIGMA.g(i).multidot.x(t-i)
where y(t) represents a filtered output digital data sequence.
Conventional circuit arrangements for implementing the convolution algorithm are illustrated in FIGS. 2 and 3 and have been described in a paper entitled "FIR Filter and Digital Signal Processing", Musen to Jikken, Special Edition, issued on Nov. 20, 1979, pp.89-96. The circuit diagram shown in FIG. 2 is a basic arrangement for performing the convolution algorithm. In FIG. 2, input terminal 30 receives a digital data sequence x(t) consisting of a plurality of coded bytes (e.g., of 16 bits per byte) obtained through an analog-to-digital (A/D) conversion of an analog signal at sampling frequency w. The sequence x(t) is fed through a delay device 31 composed of N-1 delay elements 31.sub.1 through 31.sub.N-1, each imparting a delay time T equal to the sampling period 1/F.sub.S. The outputs x(t) to x(t-N+1) of the delay elements 31.sub.1 through 31.sub.N-1 are sent to multipliers 32.sub.0 through 32.sub.N-1 each having a corresponding filter coefficient g(i) (i=0, 1, . . . , N-1) derived from a desired impulse response or frequency transfer function. The outputs of the multipliers 32.sub.0 through 32.sub.N-1 are sent to an adder 33 to give a digital output sequence y(t). Such a structure achieves the required filtering characteristics given the appropriate coefficient factors g(i). The circuit shown in FIG. 2, however, requires a large number of delay elements and multipliers to implement a convolution algorithm of higher order.
The circuit in FIG. 3 has been proposed in the previously mentioned November 1979 paper for improving the basic circuit shown in FIG. 2, and includes memories for storing an input data sequence x(t) and corresponding filter coefficients g(i). In FIG. 3, the set of coefficient data factors g(k), which are set beforehand, are stored in ROM (read-only memory) 31. These coefficient data factors g(k) are sequentially read from addresses provided by address counter 37 and the coefficient data are fed to multiplier/accumulator 33. The input signal x(t), which constitutes the other data sequence of the convolution arithmetic calculation, is supplied to input I from an external source at prescribed intervals. As shown in the drawing, the input signal x(t) may be applied to multiplier/accumulator 33 through switch 35 or to a data input terminal D.sub.IN of RAM (random access memory) 36. Switch 35 determines whether input signal x(t) is fed to multiplier/accumulator 33 directly or is stored in RAM 36 for later presentation to the accumulator. The RAM 36 stores the input signal x(t) at certain prescribed times and is normally in a read mode so as to supply the stored input signals to multiplier/accumulator 33 through switch 35. Both the designation of the operating mode (read/write) and the application of addresses to RAM 36 (via RAM Address Counter 34) are carried out by timing control circuit 32 which is operated by a software-driven microcomputer. The timing control circuit 32 also generates addresses for ROM 31 via ROM Address Counter 37 and further controls the operation mode of RAM 36 and the timing of multiplier/accumulator 33. ##EQU1## will be considered to help explain the operation of the circuit shown in FIG. 3. First, timing control circuit 32 and counters 34 and 37 indicate the addresses to enable sequential output of the coefficient data factors g(2), g(4), . . . , g(2m) stored in ROM 31 and of the input signals x(t-1), x(t-2), . . . ,x(t-m) stored in RAM 36 according to the proper correspondence between g(2k) x(t-k). These data are supplied to multiplier/accumulator 33 where corresponding elements of both sequences are successively multiplied and the products added. During this time, a R/W (designating read/write) signal from the timing control circuit 32 is at the L (low) level so RAM 36 is in the read mode. The R/W signal is also applied to a control terminal (not shown) of switch 35, so that the path of the input signal x(t) from the external source is disabled.
Before timing control circuit 32 performs the above operation, or at a suitable time during its progress, the R/W signal changes to the H (high) level, putting RAM 36 into the write mode, and setting switch 35 to connect multiplier/accumulator 33 to the external source device so that the current input signal x(t) is fed both to multiplier/accumulator 33 and to RAM 36. Timing control circuit 32 simultaneously identifies the addresses of ROM 31 and RAM 36 so that the coefficient data factor g(k) corresponding to the input signal x(t) is read out from ROM 31 and the current input signal x(t) is stored at the prescribed address in RAM 36 ready for use in the next calculation. When the convolution algorithm ##EQU2## has been performed, multiplier/accumulator 33 outputs the result of its convolution calculation in response to an output control signal from timing control circuit 32.
Thus, the conventional convolution arithmetic circuit involves storing, in prescribed locations in the memory, two sets of data relating to the convolution calculation between the input signal x(t) and the coefficient data g(k), and supplying these sequentially to a multiplier/accumulator in accordance with a correspondence relationship, all these operations being controlled by a programmed microcomputer.
The above conventional convolution arithmetic circuit has a certain flexibility in that it makes use of a programmable microcomputer, but, if it were to be applied as a digital filter in, for example, a DAD system, problems would arise regarding the processing speed of the microcomputer software rendering the convolution arithmetic circuit unable to cope with the data flow.
This problem can have very dire consequences. Specifically, in a digital filter used in a digital recording and playback unit as described above, the input signal x(t) is sampled at the sampling interval before being input sequentially, so the convolution algorithm must be performed in real time. This causes higher order calculation since the sampling frequency of the coefficient data g(k) that is used in the convolution algorithm must be fairly high, due to the need to set a transmission function, i.e., a filter characteristic, for the digital filter that will enable it to deal with signals containing a large number of high-frequency components. Since, as mentioned above, all the address signals and operations must be controlled by the programmed microcomputer, the load on the CPU (central processing unit) of the microcomputer becomes too great to carry out the arithmetical processing in the required time intervals. Such problems increase as the complexity of the calculations increase, and these problems set limits on the signal processing capabilities that can be achieved in practice using such conventional convolution arithmetic systems.